The present invention relates generally to integrated circuit (IC) fabrication. More particularly, the present invention relates to fabrication of IC features having reduced critical dimensions than is possible with conventional lithography and resolution enhancement techniques.
The semiconductor or integrated circuit (IC) industry aims to manufacture ICs with higher and higher densities of devices on a smaller chip area to achieve greater functionality and to reduce manufacturing costs. This desire for large scale integration requires continued shrinking of circuit dimensions and device features. The ability to reduce the size of structures, such as, gate lengths in field-effect transistors and the width of conductive lines, is driven by the performance of lithographic tools (e.g., wavelength of the exposure sources), resolution enhancement techniques (e.g., phase shifting masks, off-axis illumination, etc.), and photoresist materials (collectively referred to as lithographic techniques).
However, currently available lithographic techniques lack the resolution to print desirably small IC device features. Thus, various non-lithographic techniques are also employed to shrink or reduce feature dimensions after lithographic printing. One such non-lithographic technique is a resist trimming process that reduces or xe2x80x9ctrimsxe2x80x9d features patterned on a photoresist layer of a semiconductor wafer before such features are transferred onto the underlying layer(s) of the semiconductor wafer. The resist trimming process utilizes a plasma etch to remove some of the patterned photoresist material such that the critical dimensions of the patterned features are reduced.
Different types of photoresist materials exhibit different trimming performances. For example, photoresist materials designed for 193 nm lithography, e.g., photoresist materials comprising acrylate-based polymers and/or alicyclic-based polymers, have poor trimming performance in comparison with 248 nm photoresist materials, e.g., photoresist materials comprising phenolic polymers. Typical failure mechanisms during the resist trimming process for features patterned on 193 nm photoresist materials include pattern collapse, pattern bending, pattern breakage, general mechanical deformation, and/or uncontrollable photoresist erosion rates. Other photoresist materials also exhibit such failure mechanisms depending on the operating conditions of the resist trimming process (e.g., prolonged trimming time) and/or the original dimensions of the lithographically printed features on the photoresist materials.
To mitigate some of these failure mechanisms, a thinner layer of photoresist material may be disposed on the wafer for lithographic printing or pattern transfer of features from a mask or reticle. However, the initial reduction in photoresist thickness allows for less critical dimension reduction with the resist trimming process due to photoresist consumption concerns. Since the resist trimming process trims the exposed surfaces of the patterned features in both the vertical and horizontal directions (i.e., simultaneously reduces the height and width of the patterned features), by the time a desirable trimmed width has been achieved, there may not be enough height or vertical thickness remaining for the trimmed features to survive subsequent processes (e.g., an etch process for polysilicon gate formation).
Thus, there is a need for a process for enhancing the etch trimmability and etch stability of patterned photoresist features. There is a further need for a process for forming IC features having smaller critical dimensions than is possible with conventional lithographic and non-lithographic techniques. There is still a further need for a process for preventing pattern collapse, pattern bending, pattern breakage, and/or general mechanical deformation of patterned resist features during etch processing.
One exemplary embodiment relates to a method for achieving a sub-lithographic critical dimension in an integrated circuit device feature. The integrated circuit device feature is formed on a semiconductor wafer using a feature patterned on a photoresist layer. The method includes curing the feature patterned on the photoresist layer with an electron beam. The method further includes trimming the cured feature to form a trimmed feature. The sub-lithographic critical dimension of the trimmed feature is dependent on a dose of the electron beam.
Another exemplary embodiment relates to a feature patterned on a photoresist layer having enhanced etch stability and trimmability in an etch process. The feature includes a top region. The feature is formed by the process including irradiating the feature patterned on a photoresist layer with an electron beam before the etch process. At least the top region of the feature is cross-linked to the point of complete decomposition to form a cross-linked top region.
Still another exemplary embodiment relates an integrated circuit fabrication process. The process includes curing a patterned photoresist layer with an electron beam, and trimming the cured photoresist layer with a plasma etch. The process further includes transferring a pattern of the trimmed photoresist layer to the substrate. The patterned photoresist layer is disposed over a substrate. A critical dimension of the transferred pattern on the substrate has a sub-lithographic dimension and is a function of a dose of the electron beam in the curing step.